SystemVerilog mode

    string msg = $sformatf("%d + %d = %d", a, b, result);
 
1
// Literals
2
1'b0
3
1'bx
4
1'bz
5
16'hDC78
6
'hdeadbeef
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'b0011xxzz
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1234
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32'd5678
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3.4e6
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-128.7
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​
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// Macro definition
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`define BUS_WIDTH = 8;
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​
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// Module definition
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module block(
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  input                   clk,
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  input                   rst_n,
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  input  [`BUS_WIDTH-1:0] data_in,
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  output [`BUS_WIDTH-1:0] data_out
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);
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  always @(posedge clk or negedge rst_n) begin
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​
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    if (~rst_n) begin
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      data_out <= 8'b0;
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    end else begin
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      data_out <= data_in;
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    end
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    if (~rst_n)

Syntax highlighting and indentation for the Verilog and SystemVerilog languages (IEEE 1800).

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